A relaxation oscillator is known from the prior art and its basic diagram is provided in FIG. 1. Such a relaxation oscillator comprises two like modules 1, 2, each having a ramp generator 3, 4 formed by a reference current source 5, 6 and a storage capacitor 7, 8 defining a ramp voltage (Vramp1, Vramp2), a reference voltage generator 9 and a voltage comparator 10, 11 for comparing the ramp voltage (Vramp1, Vramp2) with the reference voltage (Vref). An asynchronous RS type flip-flop 12 receives the output signal of the comparator 10 of the first module at a first input (s) and the output signal of the comparator 11 of the second module 2 at a second input (r). Then as a result of the bias of the output terminals q and qb the flip-flop 12 alternately supplies control signals for charging the capacitor 7 of the first module and for charging the storage capacitor 8 of the second module. For this, each ramp generator 3, 4 is controlled by means of a switch 13, 14.
The operation of such a relaxation oscillator is described in association with FIG. 2 that shows the ramp voltages (Vramp1, Vramp2) in relation to time. In an initial stage, the switch 13 is open, the reference current source 5 charges the storage capacitor 7 by means of the reference current Iref. At the same stage, the switch 14 is closed so that the storage capacitor 8 is short-circuited and is therefore not charged. When the ramp voltage Vramp1 reaches the level of the reference voltage Vref, the voltage comparator 10 detects this and the signal that it outputs is modified so that the flip-flop 12 changes state. The output signals at terminals q and qb are inverted. Thus, switches 13 and 14 are closed and open respectively. The charge stored on the capacitor 7 is then discharged to Vss by short-circuit, while charging the capacitor 8 begins. Similarly, when the ramp voltage Vramp2 reaches the level of the reference voltage Vref, the voltage comparator 11 detects this and the signal that it outputs is modified so that the flip-flop 12 changes state. The output signals at terminals q and qb are once again inverted and the initial cycle can start again. These two charge phases successively of capacitor 7 and capacitor 8 represent an oscillation period.
Another relaxation oscillator of the prior art is described in patent document U.S. Pat. No. 6,720,836. This document describes a relaxation oscillator with current sources coupled to one another.
For radio-frequency identification applications involving RFID transponders, the consumption of current sources used in such relaxation oscillators is one of the most critical parameters. The theoretical minimum current consumption for such a relaxation oscillator is given by the formula C*Vref/T=Iref. To minimise current consumption for a set oscillation period, the storage capacitor C and the reference voltage Vref must be reduced to the full. For this purpose, it is important to note that the reference voltage Vref corresponds to the oscillation amplitude.
The existing solutions have one or more disadvantages listed below and are therefore further removed from the theoretical minimum consumption.
Firstly, an oscillator like that shown in FIG. 1 consumes the equivalent of the theoretical minimum current consumption just with the ramp generator (via the source of reference current Iref). Therefore, all the other consumer circuits will take such an oscillator further away from the theoretical minimum consumption. These other consumer circuits comprise in particular the reference voltage generator, comparators of the ramp voltage with the reference voltage.
An oscillator such as that described in patent document U.S. Pat. No. 6,720,836 has the major disadvantage of having an oscillation amplitude associated with the gate-source voltage Vgs of a CMOS type transistor that can thus not be decreased in order to reduce current consumption. Moreover, such a relaxation oscillator uses a current mirror with a size ratio of 1 to 10 between the transistors of the mirror, and this requires a significant surface over an integrated circuit.
In addition, it must also be noted that the voltage amplitude is only in theory equal to Vref. In reality, a phenomenon of overrun occurs in the switching phases as a result of the reaction time of the comparators. This is the case in particular in oscillator solutions using transistors that do not operate fully in saturated mode.
Finally, the minimum value for the storage capacitor is determined in particular by the value of the interference capacitor on the upper plate of the storage capacitor. These interference capacitors come from metal connections and other devices connected to the upper plate of the storage capacitor. Previous solutions based in particular on the Vittoz loop connect numerous or extensive devices to this capacitor. The operation of these devices in weak inversion increases the capacitor compared to an operation of these devices in strong inversion. Therefore, it will be important to ensure that a limited storage capacitor is maintained.